Job Description

CPU Verification Engineer - Senior and Principal level

Multi UK locations

Growing UK Division

I am looking for Verification Engineers at Senior and Principal level to join my clients fast-growing CPU Hardware team. They are expanding their CPU IP development from internal use to support an extensive portfolio offering highly competitive RISC-V CPUs.

Their mission is to create through constant innovation the best-in-class RISC-V CPUs for a wide range of market segments and applications.

By joining the team, you will have the opportunity to exercise your skills on cutting-edge designs, work on key building blocks for market-leading chips and deliver significant impact to the future success of their wider team.

You will:

• Be responsible for the delivery of all verification activities related to a CPU component or sub-system from early stages of verification planning to sign-off
• Create verification plans, develop and maintain testbench components,
• Track and report verification metrics and closure
• Participate in all stages of design specification definition providing feedback from the verification perspective
• Be able to influence and advance CPU verification methodology
• Have the opportunity to lead, coach and mentor other members of the team
• Participate in design and verification reviews and recommend improvements

For this role you will;

• Have a proven track record of developing verification environments for complex RTL designs
• Have excellent understanding of constrained-random verification methodology and challenges of verification closure
• Be confident in defining verification requirements, and work out the implementation approach and details of a testbench
• Be able to do root-cause analysis of complex issues and resolve them in a timely manner
• Have excellent knowledge of SystemVerilog and UVM

You might also have:

• Experience leading small teams
• Knowledge of CPU/GPU architecture
• Knowledge of standard bus protocols (e.g., AMBA5 CHI, AMBA4 ACE or AXI)
• Experience in wider verification technologies, such formal property-based verification and code mutatio

For more information please contact Rachel Mason

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